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Application Note 1165
TABLE 2. INSTRUCTION FRAME FOR READING MSCR AND
STAT
signal is provided in the XSD Access tab as an option of the
Send button. When this option is selected, the host sends
BYTE
010
ADDRESS
0000,0000
BANK
01
OPCODE
01
CS
0
out a ‘power-on break’ before sending the instruction frame.
Figure 14 illustrate the two ‘break’ signals. The narrow one
was sent by the host and the wider one was the one returned
Power-on Break
When the ISL6296 is in sleep mode, the host needs to send
a ‘break’ signal to wake up the ISL6296. A ‘break’ signal is a
pulse wider than 1BT. When coming out of the sleep mode,
the ISL6296 sends a ‘break’ as well. The two ‘break’ signals
overlap with each other (merged) and appear to be one
pulse. The ‘break’ signal from the ISL6296 is 1.391BT wide,
therefore, contains the information for the XSD bus speed
(= 1/BT) in the ISL6296. In order to see the ‘break’ signal
from the ISL6296, a special narrow ‘break’ (power-on break)
from the ISL6296 (approximately 480 μ s). From the 480 μ s
‘break’ signal, the BT can be calculated as
BT = 480 μ s/1.391 = 345 μ s
or baud rate is
Baud Rate = 1/BT = 2.90 kbps
Error ‘Break’
When an error occurs during the XSD transaction, a ‘break’
signal is sent by the ISL6296. Figure 15 shows the waveform.
A message, as shown in Figure 2, pops up in this case.
A
B
0
1
0
0
0
0
1
0
1
0
0101000000000010 00000011 00000000
FIGURE 12. CAPTURED SCOPE WAVEFORMS TO SHOW ‘1’
AND ‘0’ OF XSD BUS SIGNALS
FIGURE 13. CAPTURED SCOPE WAVEFORMS WHEN
READING THE MSCR AND STAT REGISTERS
A falling edge sets the start of a bit time and the timing of the rising
edge determines the bit value.
Break
from
ISL6296
Vertical: 1V/div
Horizontal: 200us/div
FIGURE 14. POWER-ON BREAK SIGNAL TO WAKE-UP THE
ISL6296 FROM SLEEP MODE
8
FIGURE 15. ‘BREAK’ SIGNAL SENT BY ISL6296 DUE TO A
BUS TRANSACTION ERROR
AN1165.1
July 14, 2009
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